Current designs for a large cache that comprises many individual instances of Embedded Dynamic Random Access Memory (EDRAM) macros generally pose problems that were not encountered by prior Static Random Access Memory (SRAM) based designs. In particular, EDRAM devices have programmable performance parameters such as access time and busy time that are used to balance manufacturing yield with improved performance. While the ability to vary these parameters provides operational flexibility, this ability results in additional complexity with regard to modeling the availability of the cache resources. However, current designs generally do not take into account these programmable performance parameters, which results in inefficient utilization of cache resources.